The present invention relates generally to circuitry and methods for stacking integrated circuit die, and more particularly to a circuit configuration and method which allow controlling input/output functions of stacked integrated circuit die by means of simple bonding connections in the stacked die arrangement.
In some applications, it is conventional to “stack” integrated circuit die (i.e., integrated circuit die), one on top of the other, in order to conserve area on a printed circuit board and/or to improve circuit performance. Also, in some applications it is conventional to provide a “daisy chained” connection of outputs of various digital circuits wherein the output signal of a first digital circuit appears on a daisy chained output during a first time frame and the digital output signal of a second digital circuit appears on the daisy chained output terminal of the first digital circuit during the next time frame, in order to reduce the number of output terminals and complexity of associated circuitry that would be required for reading the data on numerous output terminals.
FIG. 1A illustrates a partial section view of an assembly 1 including an exposed thermal pad 2, a bottom die 4 attached to the upper surface of the thermal pad 2, one or more bonding wires 7 connected between one or more bonding pads (not shown) on the upper peripheral surface of bottom die 4 and pads or package leads of an ordinary package lead frame 3 In some cases, one or more dimensions of the top die 6 are smaller than those of bottom die 4, as shown. An insulating spacer, typically composed of silicon roughly 10 mills thick, attaches a top die 6 to the upper surface of bottom die 4 in such manner as to expose the peripheral bonding pads (not shown) on the upper peripheral surface of bottom die 4 and allow the bonding wires 7 to extend from various peripheral exposed bonding pads of bottom die 4 to the various package leads 3. Preferably, various bonding pads on the upper peripheral surface of top die 6 are connected by bonding wires 8 to various pads or package pins of package lead frame 3. Molding or encapsulating compound 45 encapsulates the structure as shown.
FIG. 1B shows a prior art arrangement of three integrated circuit chips 101,102, and 103 each directly attached to the surface of a printed circuit board 100, wherein each of the three chips includes an ADC (analog-to-digital converter) 105A, 105B, and 105C, respectively. Analog input signals ANALOGIN1, ANALOGIN2 and ANALOGIN3 on conductors 107, 108, and 109, respectively, are provided as inputs to the three ADCs, respectively.
Each of the three chips 101, 102, and 103 also includes conventional daisy chain circuitry including serial data shift registers 106A, 106B and 106C for receiving the digital outputs DOUT of ADCs 105A, 105B and 105C, respectively. The digital outputs of the three ADCs 105 are coupled to parallel digital inputs of the serial data shift registers 106A, 106B and 106C, respectively. Each of the three data registers is clocked by a data clock signal DCLK. The digital serial input DIN of data register 106A of the first chip 101 is connected to ground so that only “0”s can be serially shifted into it from left to right. The serial digital output DOUT of data register 106A is connected to the serial digital input DIN of data register 106B, the serial digital output DOUT of which is connected to DIN of data register 106C. DOUT of data register 106C is connected to a serial data output conductor 112.
After the three analog input signals on conductors 107, 108, and 109 have been converted to digital values which have been loaded via three digital buses or channels into the three data registers 106A, 106B, and 106C respectively, the three digital conversion result output words can be serially shifted out of data output conductor 112 in response to the DCLK clock signal. As the three output words are shifted from left to right in FIG. 1B, they are replaced by “0”s.
The prior art shown in FIG. 1B requires much more printed circuit board area than is desirable.
It would be very desirable to have a more efficient technique and structure for daisy chaining a number of digital data channels using stacking die technology.
Thus, there is an unmet need for an integrated circuit die-stacking configuration that minimizes the number of bonding pads required on each integrated circuit die.
There is another unmet need for an integrated circuit die-stacking configuration that reduces or minimizes circuit and system delay due to capacitive loading effects of unused output pads.
There is another unmet need for an integrated circuit die-stacking configuration and associated circuitry in the die that disables the driving of unused bonding pads that could cause noise coupling to nearby analog circuits.